Data Path Delays

Time-Stamping and Time Synchronization

Intel® PAC
Napatech SmartNIC
Content Type
User Guide

In this chapter

This chapter describes delays in the data path, and explains how compensation can be made for both RX and TX delays using stored results from path latency measurements.
Note: This chapter does not apply to the Intel® PAC with Intel® Arria® 10 GX FPGA.