IEEE 1588 PTP Slave with PPS Synchronization

The figure shows an NT SmartNIC configured in PTP slave mode using PPS phase synchronization for increased accuracy. This is obtained by using the PtpPpsSampling parameter (see Configuring PTP PPS Sampling Mode) and the Napatech pps_ptp tool (see DN-0449). When the PtpPpsSampling parameter is set to ENABLE, the PHY clock and the FPGA clock are separated. The FPGA clock is still used for time-stamping of the frames received on the front ports and can be configured to be synchronized to the grandmaster PPS output. The PHY clock can be configured to be synchronized to the PTP signal from the IEEE 1588 grandmaster. This allows the time of day to be obtained from the PHY clock, while the accuracy of the free-running FPGA clock is increased due to the PPS synchronization. This is useful, for instance, if the routers and switches in the IEEE 1588 network are not PTP-aware.