Frame Processing

Napatech Link-Capture™ Software Features
Platform
Napatech SmartNIC
Content Type
Feature Description
Capture Software Version
Link™ Capture Software 12.16

Frames are processed by the IP blocks in the SmartNICs.

IP blocks for frame processing

The figure below shows a high-level diagram of the frame processing pipeline. The received frames are processed by the functional IP blocks in the sequence shown in the figure below.

Figure 1. Frame processing pipeline
Page-1 Sheet.1 Frame Decoder Frame Decoder Sheet.2 Categorizer & Filter Categorizer & Filter Sheet.3 Hasher Hasher Sheet.4 Correlation Key Correlation Key Sheet.5 Deduplication Deduplication Sheet.6 IP Fragment Handling IP Fragment Handling Sheet.7 Packet Masker Packet Masker Sheet.8 Header Stripper Header Stripper Sheet.9 VLAN Insert VLAN Insert Sheet.10 Local Retransmit TAP Local Retransmit TAP Sheet.11 Slicer Slicer Sheet.12 Slicer Slicer Sheet.13 Load Distributor (Queue Select) Load Distributor(Queue Select) Sheet.14 Rx Buffer Handler Rx Buffer Handler Sheet.15 SDRAM SDRAM Sheet.16 Sheet.17 PCIe PCIe Sheet.20 Tx Scheduler Tx Scheduler Sheet.21 Tx Buffer Handler Tx Buffer Handler Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Rx Rx Sheet.64 Tx Tx Sheet.65 Sheet.66 Dynamic connector

This table shows supported IP blocks for each SmartNIC.

Note: Table legend:
  • FPGA image types
    • CR1: Capture CR1 image
    • CR2: Capture CR2 image
    • FM1: Capture FM1 image
    • SLB: Capture SLB image
    • TM1: Capture TM1 image
  • G: Gbit/s
  • X: Supported.
  • –: Not supported.
Table 1. Supported IP blocks
IP Block NT400D13 NT400D11 NT200A02 NT100A01 NT50B01 NT40A11 NT40A01 NT40E3-4-PTP NT20E3-2-PTP
2×200G TM1 2×100G TM1 2×40G TM1 8×25/10G TM1 2×100G FM1 2×100G TM1 2×40G FM1 2×40G TM1 8×25/10G FM1 8×25/10G TM1 2×100G CR1 2×100G FM1 2×100G TM 2×40G  CR1 2×40G FM1 2×40G TM1 2×40G SLB 4×25/10G CR1 2×25/10G CR1 2×25/10G TM1 8×10G TM1 8×10G FM1 8×10G SLB 2×10/1G CR1 4×25/10G FM1 4×25/10G TM1 4×10/1G FM1 4×10/1G TM1 2×25/10G TM1 2×10/1G TM1 4×10/1G CR2 4×10/1G CR1 4×10/1G SLB 4×1G CR1 4×10/1G CR2 4×10/1G CR1 2×10/1G CR1
Frame decoder X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Categorizer and filter X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Hasher X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Correlation key X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X – X X X X
Deduplication X X X X X X X X X X X X X X – X X X X X X – X X – X – X X X X X – X X X X
Load distributor X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
IP fragment handling X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X – X X X – X X
Packet masker X X X X – X – X – X X – – X – – – X X – X – – X – X – X – – – – – – – – –
Header stripper X X X X – X – X – X X – – X – – – X X – X – – X – X – X – – – – – – – – –
VLAN insert X X X X – X – X – X X – – X – – – X X – X – – X – X – X – – – – – – – – –
Local retransmit X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X – X X X – X
Slicer X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Slicer on locally retransmitted frames X X X X – X – X – X X X X X X X – X X X X X – X – – – – – – – – – – – – –
Rx buffer handler X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Tx buffer handler X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Tx scheduler X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X