Updating the FPGA

Use this information to program a new FPGA image with one Altera™ FPGA Download Cable II.

Before you begin

Make sure that you have:

An Altera™ FPGA Download Cable II.
A Passive FPGA Download Cable converter box.
Installed the Quartus® Prime Pro Programmer. For information on how to install the Quartus® Prime Pro Programmer, consult the Altera™ documentation.
Placed the Napatech package for programming DPUs/SmartNICs on the remote server, where the Altera™ FPGA Download Cable II is connected to.

Note: Do not program the FPGA/BMC on the same system that is hosting the DPU/SmartNIC as this may cause the host to crash or reboot during programming.

About this task

For updating the FPGA, a JTAG indirect configuration file (.jic) is used. After firmware images for the BMC and the .jic file for the FPGA are programmed, it is required to power cycle the server, where the DPU/SmartNIC is installed.

Note: The following prompts are used to indicate which part of the system to run the provided commands on.

host#: The server, where the DPU/SmartNIC is installed.
soc#: The SoC on the DPU/SmartNIC.
prog#: The remote server, where the Altera™ FPGA Download Cable II units are connected to.

Procedure

Attach the Altera™ FPGA Download Cable II to the connector of the converter box for the FPGA chain as illustrated in the following figure.

This figure shows that the Altera™ FPGA Download Cable II is connected to the converter box for programming the FPGA.
Attach the other end of the converter box to the JTAG programming interface on the DPU/SmartNIC.
For information on the JTAG programming interface of the corresponding DPU/SmartNIC, refer to the relevant documentation.
- F207xX DPUs: Connecting a JTAG Programmer in DN-1374.
- F307xX DPUs: Connecting a JTAG Programmer in DN-1409.
- N3070X SmartNICs: Connecting a JTAG Programmer in DN-1410.
Connect a USB cable to the Altera™ FPGA Download Cable II.
Install the DPU or the SmartNIC in a server if it is not installed.
For detailed information for the corresponding DPU/SmartNIC, see the relevant documentation.
- F207xX DPUs: Install in a Server in DN-1374.
- F307xX DPUs: Install in a Server in DN-1409.
- N3070X SmartNICs: Install in a Server in DN-1410.
Attach the other end of the USB cable to a remote server.
On the remote server, unpack the corresponding Napatech package for programming the DPUs/SmartNICs.
For example:
```
prog# tar -xzvf ipu_fw-1.0.0-eb49d0c7af8-linux.tar.gz
```
Export the path to the Quartus® Prime Pro Programmer.
For example:
```
prog# export QUARTUS_ROOTDIR="/tools/linux/intel/quartus/22.1/pro/quartus"
```

Disable the pmci-main application on the DPU/SmartNIC.

The pmci-main application is a firmware running on the DPU/SmartNIC and needs to be stopped before programming the FPGA image. To stop pmci-main, execute the following command:

prog# ${QUARTUS_ROOTDIR}/bin/nios2-gdb-server -c <cable_number> -i 2 --stop

where:

-c/--cable: Specifies the cable number, indicating which chain is connected to the FPGA.
i/--instance 2: Specifies the instance value of the NIOS II processor on which the pmci-main application is running; this value is always 2.

To retrieve the -c details, run the following command:

prog# ${QUARTUS_ROOTDIR}/bin/jtagconfig -n

An output example:

1) USB-BlasterII [1-6.2]
  031050DD   10M50DA(.|ES)/10M50DC
    Design hash    7C3B922AD2B2EC5A183F
    + Node 0C206E00  JTAG PHY #0
  031050DD   10M50DA(.|ES)/10M50DC
    Design hash    E8F830D73191E60E68D2
    + Node 0C206E00  JTAG PHY #0
    + Node 19104600  Nios II #0

2) USB-BlasterII [1-6.3]
  034130DD   AGFA027R25A(.|R0)
    Design hash    093C51B823C428F00497
    + Node 19104600  Nios II #0
…
…

In this output, AGFA027R25A(.|R0) represents the FPGA device, indicating that cable 2 is connected to the FPGA.

The following output is another example that displays AGIC041R29D(B|C), indicating cable 1 is connected to the FPGA.

1) USB-BlasterII [1-6.2]
  634B70DD   AGIC041R29D(B|C)
    Design hash    ABDB0A65E35F84F5A43E
    + Node 00486E00  Source/Probe #0
…
… 
2) USB-BlasterII [1-6.3]
  031050DD   10M50DA(.|ES)/10M50DC
    Design hash    F7653DA496BF0DF924EF
    + Node 0C206E00  JTAG PHY #0
    + Node 19104600  Nios II #0
  031050DD   10M50DA(.|ES)/10M50DC
    Design hash    48075B1717E74BF59952
    + Node 0C206E00  JTAG PHY #0
    + Node 19104600  Nios II #0

Locate the nt_jtag_pgm.sh script in the package.
For example:
```
prog# cd ipu_fw/bin/
```

Update the FPGA with a .jic file.

If nt_jtag_pgm.sh is not executable, change the permissions to make it executable as follows.

prog# chmod +x nt_jtag_pgm.sh

Locate the target FPGA image. A command example for an F2070X DPU.

prog# ./nt_jtag_pgm.sh --fpga=/images/INTEL-F2070X-7106/f2070x_chip.jic

A command example for an F2071X DPU.

prog# ./nt_jtag_pgm.sh --fpga=/images/INTEL-F2070X-7107/f2070x_chip.jic

An output example:

--------------------------------------------------------------------------------
Using these environment variable:
  QUARTUS_ROOTDIR  = /tools/linux/intel/quartus/22.1/pro/quartus
  QUARTUS_BIN      = /tools/linux/intel/quartus/22.1/pro/quartus/bin
  SYSCON_BIN       = /tools/linux/intel/quartus/22.1/pro/quartus/../syscon/bin
--------------------------------------------------------------------------------
BMC files to program:
  bmcm_pof    = not_specified
  bmcd_pof    = not_specified
  usr_app     = not_specified
  factory_app = not_specified
FPGA file to program:
  fpga_img    = /images/INTEL-F2070X-7107/f2070x_chip.jic
--------------------------------------------------------------------------------
Removing FTDI driver (load agin: sudo modprobe ftdi_sio)
JTAG cable detect found a cable with an Agilex device:
  Agilex JTAG cable = 2
  Detected SKU1 HW  = Agilex 027 device
WARNING: FPGA image for SKU1 is expected to be called 9635|7101|7103|7105|7107. Are you sure you want to proceed? (Enter 'yes' to continue): yes

Enter yes to continue programming the FPGA image.

An output example after programming the FPGA image is complete:

…
…
Info: Command: quartus_pgm -c 2 -m jtag -o p;/images/INTEL-F2070X-7107/f2070x_chip.jic@1 -o s;PHY1G@2
Info (213045): Using programming cable "USB-BlasterII [1-13.2]"
Info (213011): Using programming file /images/INTEL-F2070X-7107/f2070x_chip.jic with checksum 0x3745AEA6 for device AGFA027R25A@1
Info (209060): Started Programmer operation at Thu Apr 18 09:53:23 2024
Info (19094): Erasing flash 1 at device index 1
Info (19096): Programming flash 1 at device index 1
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Thu Apr 18 10:04:33 2024
Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 1346 megabytes
    Info: Processing ended: Thu Apr 18 10:04:33 2024
    Info: Elapsed time: 00:11:18
    Info: System process ID: 2390
INFO: Power cycle host to load new Agilex image from flash

Power cycle the server, where the DPU/SmartNIC is installed.
For example:
```
host# shutdown -h now
```
It is important to power off the server completely to ensure the PCIe 3.3 V power is off. To do this, power the server down, disconnect the server from all power cables, wait for at least 10 seconds, reinsert power cables and power the server up again.

Detect PCIe devices.

For example:

host# lspci -d 1af4:

An output example on the server where the DPU is installed.

0d:00.0 Ethernet controller: Red Hat, Inc. Virtio network device
0d:00.1 Ethernet controller: Red Hat, Inc. Virtio network device
0d:00.2 Ethernet controller: Red Hat, Inc. Virtio network device
0d:00.3 Ethernet controller: Red Hat, Inc. Virtio network device

An output example on the SoC of the DPU.

soc# lspci -d 1af4:

15:00.1 Ethernet controller: Red Hat, Inc. Virtio network device
15:00.2 Ethernet controller: Red Hat, Inc. Virtio network device
15:00.4 Ethernet controller: Red Hat, Inc. Virtio network device
15:00.5 Ethernet controller: Red Hat, Inc. Virtio network device
15:00.6 Ethernet controller: Red Hat, Inc. Virtio network device
15:00.7 Ethernet controller: Red Hat, Inc. Virtio network device