Compensating for Signal Delays

Time-Stamping and Time Synchronization

Intel® PAC
Napatech SmartNIC
Content Type
User Guide
Capture Software Version
Link™ Capture Software 12.9

In this section

This section describes signal delays in cables and SmartNICs.

Signal delay contributors

Signal delay contributors are time synchronization cabling, the master NT SmartNIC output circuit, the slave NT SmartNIC input circuit, and delays from equipment in the signaling path between the master and slave. Equipment in the signaling path can be one or more NT SmartNICs configured for daisy-chaining. This figure is the reference model for signal delay calculations.

Reference model for signal delay calculations

Actual signal delays

This table defines the delay contribution from cables and devices in the signal path. The table can be used to calculate the total delay compensation needed for a slave. There can be multiple daisy chain devices and cables in the signal path.

Delay Contributor Delay (in ns)
NT200A02 and NT100A01 NT40A01, NT40E3-4-PTP and NT20E3-2-PTP
TS output circuit delay (TS_Out_Delay) INT: 9 INT: 8
EXT: 10 EXT: 9
TS input circuit delay (TS_In_Delay) INT: 7 INT: 6
EXT: 9 EXT: 8
Daisy chain delay (Daisy_Chain_Delay) INT to INT: 15 INT to INT: 14
INT to EXT: 16 INT to EXT: 15
EXT to INT: 16 EXT to INT: 15
Cable delay (Cable_Delay) 5 per meter

Offset compensation

The total time synchronization signal delay can be compensated by configuring a time offset in nanoseconds in the slave NT SmartNIC. This is done using the TimeSyncTimeOffset parameter (see DN-0449). The time offset is applied to the time stamp clock when synchronizing to a master NT SmartNIC.

ntservice.ini code line

The syntax for the ntservice.ini code line configuring the time stamp offset is:

'TimeSyncTimeOffset' '=' ( '0' | '1' |  '2' |  ... |  '1000000' )



Default value

This table shows the default value.

Parameter Default Value
TimeSyncTimeOffset 0