Daisy Chain with Hardware Synchronization

Time-Stamping and Time Synchronization

Platform
Intel® PAC
Napatech SmartNIC
Content Type
User Guide
Capture Software Version
Link™ Capture Software 12.10

Illustration

This figure shows a PTP daisy chain configuration with hardware-based synchronization of the second and the third NT SmartNIC in the chain.

PTP daisy chain configuration with hardware-based synchronization of the second and the third SmartNIC in the chain

NT SmartNIC #1 is synchronized to the PTP grandmaster reference clock. The time stamp clock of NT SmartNIC #1, provided via the output time synchronization connector (TS Out), is used as reference for NT SmartNIC #2 and NT SmartNIC #3.

NT SmartNICs #2 and #3 both repeat the NT-TS signal from the input time synchronization connector (TS In) to the output time synchronization connector (TS Out); and synchronize the time stamp clock of the SmartNIC to the NT-TS signal received on the input time synchronization connector (hardware time synchronization).

Delay compensations must be made for NT SmartNICs #1, #2 and #3. See Compensating for Signal Delays for details on cable delay.

ntservice.ini configuration

These ntservice.ini code lines configure NT SmartNIC #1 for the setup in Illustration.

TimeSyncReferencePriority=PTP,FreeRun
TimeSyncConnectorInt2=NttsOut

These ntservice.ini code lines configure NT SmartNIC #2 for the setup in Illustration.

TimeSyncConnectorInt1=NttsIn
TimeSyncReferencePriority=Int1,FreeRun
TimeSyncConnectorInt2=RepeatInt1

These ntservice.ini code lines configure NT SmartNIC #3 for the setup in Illustration.

TimeSyncConnectorInt1=NttsIn
TimeSyncReferencePriority=Int1,FreeRun