Feature Set N-ANL11

product_line_custom: Napatech SmartNIC
category: Feature Description

Notices
Modification History
Introduction
Terminology
Packets and Frames
Ports, Flows, Host Buffers and Streams
Software and FPGA Images
Monitoring Capabilities
Packet Descriptors
100 Gbit/s, 40 Gbit/s, 10 Gbit/s MAC and 1 Gbit/s / 10 Gbit/s MAC
Port Merging
Time-Stamping and Time Synchronization
Features
Time Stamp Features
Time Synchronization Features
Frame Decoding
Features
Frame Classification
ISL Classification
Outer VLAN Classification
Outer MPLS Classification
Outer Ethernet Classification
Layer 3 Classification
Layer 4 Classification
Tunnel Type Classification
Inner VLAN Classification
Inner MPLS Classification
Inner Ethernet Classification
Inner Layer 3 Classification
Inner Layer 4 Classification
Size Classification
Error Indications
Filtering
Introduction
Frame Decoder
Pattern Compare Function
Protocol Match Function
Length Compare Function
Error Match Function
Key Test, Key Match and IP Match Function
Slice Function
Packet Coloring
Correlation Key
Overview
Configuration
Example
Slicing
Hash Value Generation
Hash Calculation
Dynamic Hash Key Selection
Overview
Valid and Invalid Hash Keys
Hash Key Masks
Tuple Swap
Hash Key Types
Hash Key Type 0: Hash Disabled
Hash Key Type 2: Last MPLS Label
Hash Key Type 3: All MPLS Labels
Hash Key Type 4: 2-Tuple
Hash Key Type 5: 2-Tuple Sorted
Hash Key Type 6: Last VLAN ID
Hash Key Type 7: All VLAN IDs
Hash Key Type 8: 5-Tuple
Hash Key Type 9: 5-Tuple Sorted
Hash Key Type 10: 3-Tuple GREv0
Hash Key Type 11: 3-Tuple GREv0 Sorted
Hash Key Type 12: 5-Tuple SCTP
Hash Key Type 13: 5-Tuple SCTP Sorted
Hash Key Type 14: 3-Tuple GTPv0
Hash Key Type 15: 3-Tuple GTPv0 Sorted
Hash Key Type 16: 3-Tuple GTPv1/GTPv2
Hash Key Type 17: 3-Tuple GTPv1/GTPv2 Sorted
Hash Key Type 18: Inner 2-Tuple
Hash Key Type 19: Inner 2-Tuple Sorted
Hash Key Type 20: Inner 5-Tuple
Hash Key Type 21: Inner 5-Tuple Sorted
Hash Key Type 30: IP Fragment Tuple
Hash Key Type 31: Round-Robin
Multi-CPU Distribution
Multi-CPU Distribution Functionality
Configuration
Definition of Streams
Defining Streams Using Filter Logic
Defining Streams Using Hash Keys
Defining Streams Using both Filter Logic and Hash Keys
IP Fragment Handling
Introduction
Datagram Lookup Table
Normal Flow
Exception Flow
Fragmentation Information from Extended Descriptor Macros
Information Inherited from First Fragments
NTPL Configuration Settings
Local Retransmission and Line Loopback
Local Retransmission
Local Retransmission with Embedded Time Stamp
Line Loopback
Host-Based Transmission
TX Architecture
In-Line Functionality
Transmit on Time Stamp
Overview
Exceptions
Synchronized Transmit on Time Stamp on Multiple SmartNICs
Configuration
Example
Limitations
Limited Host-Based Transmission
Buffer System
Onboard SDRAM
Bandwidth Allocation for Transfer of Frames to Host
Statistics
Features
Statistics Features
Frame Characteristics
Statistic Counters
Port Counters
Color Counters
Stream ID Counters
Correlate Color Counters and Stream ID Counters
QPI Bypass and CPU Socket Load Balancing
QPI Bypass
CPU Socket Load Balancing
PCI Express Gen3 Controller
Flash and Flash Controller
Flash Controller
FPGA Load

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