PPS Time Synchronization

Time-Stamping and Time Synchronization

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Intel® PAC
Napatech SmartNIC
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User Guide

Limitation

This subsection does not apply to the Intel® PAC with Intel® Arria® 10 GX FPGA.

Description

PPS (pulse-per-second) time synchronization (see PPS/TTL signal) is absolute or relative time synchronization between a 3rd-party time device and an NT SmartNIC. The synchronization can be either SmartNIC clock synchronization to a PPS time reference (described in most of PPS Time Synchronization), or synchronization of third-party equipment to SmartNIC clock reference (described in Synchronization of third-party equipment to SmartNIC clock reference).
Note: PPS time synchronization requires activation from an application.

SmartNIC clock synchronization to a PPS time reference

Napatech supports synchronization to an EndRun Præcis Cf CDMA receiver, to an EndRun Præcis II CDMA receiver, to an Oregano SYN1588 PCIe NIC (IEEE 1588 / PTP) and to a Microsemi SyncServer®.

Only the precise PPS second tick is carried over the cabling. The time-of-day information is provided via another communication path, for instance a serial cable to the time device, or via the PCI bus if the time device is a PCI type device. The server OS time can also be used as the reference for time-of-day information.

Relative synchronization

The SmartNIC time stamp clock rate can be in relative synchronization (phase and frequency synchronization) to the clock rate of any external PPS time source complying with the specifications of the NT SmartNIC time synchronization input interface in Time Synchronization Input Interface.

Absolute synchronization

The SmartNIC time stamp clock rate can be in absolute synchronization (including time of day) to the UTC time from:

  • A CDMA time reference when connected to an EndRun Præcis Cf CDMA receiver, an EndRun Præcis II CDMA receiver or a Microsemi SyncServer®
  • IEEE 1588 / PTP time reference when connected to an Oregano SYN1588 PCIe NIC or a Microsemi SyncServer®
    Note: Napatech NT SmartNICs are compatible with Oregano SYN1588 PCIe NIC version V 1.1.22 or higher.
  • Other time references

PPS daisy chain support

An incoming PPS/TTL signal on an input time synchronization connector can be repeated to one or two output time synchronization connectors. The PPS timing is retained from the input to the outputs.

A single PPS time source output can synchronize multiple NT SmartNICs (with no need for external PPS distribution equipment).

NT SmartNICs can be connected in a daisy chain to relay the PPS signal from one SmartNIC to the next.

Detecting false PPS input signals

When a connector is configured as a PPS input connector, the incoming signal is checked in the FPGA to make sure that it is a proper PPS signal. If the signal is not within the predefined limits, it is considered invalid and the API will behave as if no signal were present.

Converter cables

Converter cables for connecting 3rd-party PPS time equipment to NT SmartNICs are available (see DN-0186).

Clock sampling

The sampling function of the SmartNIC time stamp clock provides the basis for all PPS features. This figure shows the principles of SmartNIC time stamp clock sampling.

SmartNIC time stamp clock sampling flows between the time device and server

Most time devices provide a PPS/TTL output signal which is synchronized to its local clock. The rising edge of the PPS/TTL output signal indicates a clock transition to the next second. Upon each of the second ticks (1.), the time device generates a PPS/TTL pulse (2.).

On the rising edge of the PPS input signal, the SmartNIC time stamp clock is sampled (3.) and stored (4.) in a SmartNIC register. This register is stable until the next rising edge of the PPS/TTL input signal, that is, stable within the next second.

The application can read the time device clock time (5.). This together with the sampled SmartNIC time stamp clock (6.) are used by the NT SmartNIC driver to calculate the SmartNIC time stamp clock skew (7.). The driver can adjust the SmartNIC time stamp clock (8.) based on the skew calculation.

Convergence time

The SmartNIC time stamp clock synchronization algorithm runs a control loop once a second (PPS) to measure and adjust the time stamp clock. The convergence time from system start-up to SmartNIC synchronization is below 2 minutes.

PPS-triggered SmartNIC clock sampling

PPS-triggered SmartNIC clock sampling can be used for software-based time stamp correction or for verification purposes. The time stamp clocks for multiple synchronized SmartNICs in a server can be sampled simultaneously.

Synchronization of third-party equipment to SmartNIC clock reference

Napatech SmartNICs can be configured to output a PPS pulse representing the phase (second tick) of the time stamp clock. The PPS output enables synchronization of third-party equipment to the SmartNIC time stamp clock (see Synchronization of Third-Party Equipment to SmartNIC Clock Reference).

Guideline

PPS time synchronization is to be used for scenarios involving 3rd-party-time-device-to-NT-SmartNIC time synchronization.