Feature Overview

Time-Stamping and Time Synchronization

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Intel® PAC
Napatech SmartNIC
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User Guide

Limitation

This section does not apply to the Intel® PAC with Intel® Arria® 10 GX FPGA.

Introduction

All NT SmartNICs provide features for clock synchronization. Multiple NT SmartNICs can be synchronized to a master SmartNIC or to a third-party time reference.

Time synchronization connectors

NT SmartNICs have external and internal time synchronization connectors that can be configured for input or output. This enables external or internal cabling between SmartNICs and time references.

External time references

An NT SmartNIC can be synchronized to an external clock via the PCI bus. NT SmartNICs can also be synchronized via a time synchronization connector.

The external time reference can be:
  • The host OS time (via the PCI bus)
  • Another NT SmartNIC (via an internal time synchronization connector)
  • A CDMA (code division multiple access) receiver (via an EndRun Præcis Cf CDMA receiver or an EndRun Præcis II CDMA receiver)
  • An IEEE 1588-2008 PTP v2 master
  • An IEEE 1588 client (via an Oregano SYN1588 PCIe NIC)
  • A Microsemi SyncServer®
  • Other 3rd-party PPS equipment fulfilling the requirements in Time Synchronization Input Interface

Time reference priorities, failover and fallback

NT SmartNICs can automatically switch between time references according to a configurable prioritized list (see Time synchronization time reference priority list). When a time reference is lost, the SmartNIC fails over to the next available reference in the list. If polling, which takes place every 15 seconds, reveals that the original time reference is recovered, the SmartNIC falls back to this reference.

Daisy-chaining of SmartNICs

An NT SmartNIC can relay a time synchronization signal from one input time synchronization connector to one or two output time synchronization connectors. This enables daisy-chaining of a time synchronization signal between NT SmartNICs.
Note: For PTP synchronization NT-TS signals are used for daisy-chaining.

The daisy chain feature enables synchronization of multiple NT SmartNICs from a single time reference without the need for any additional hardware. The SmartNICs are connected in a daisy chain with a single cable between SmartNIC pairs in the chain.

The time synchronization signal is regenerated (repeated) by the NT SmartNIC, so there is no loss of signal down the chain. Each SmartNIC in the chain introduces a fixed delay of the time synchronization signal. See PPS Time Synchronization System Configurations for examples of system configuration.

Time synchronization signal delay

When the time synchronization signal propagates from the time reference to an NT SmartNIC, each cable and device in the signal path causes a signal delay. Delays are introduced in the NT SmartNIC TS output and input driver circuit, and in the daisy chain. The total delay applied to the time synchronization signal can be compensated in the NT SmartNIC. Signal delays and configuration of signal delay compensation are described in more detail in Compensating for Signal Delays.

Time synchronization events

When a time synchronization event occurs in the event stream, the SmartNIC driver generates a driver log entry. A time synchronization event occurs, for instance, if the time synchronization reference is lost, if a SmartNIC is no longer in synchronization, if the PTP state changes or if the time stamp clock is set.

Merging of frames from different SmartNICs

When two or more SmartNICs are synchronized, captured frames from the SmartNICs can be merged in time stamp order.
Note: For this to work the time synchronization parameters must be set appropriately (see Time-Stamping and Time Synchronization Configuration). If time jumps are allowed to maintain synchronization with a reference clock, and there is a jump backwards in time, merge errors may appear in the NTAPI. If merge errors are unacceptable, time jumps must be disabled all together for each SmartNIC involved.

Synchronized transfer of block statistics

When two or more SmartNICs are synchronized, block statistics are transferred synchronously from the SmartNICs to the host. This ensures consistent counter sets when handling data from multiple SmartNICs in absolute synchronization.