Time Synchronization Input Interface

Time-Stamping and Time Synchronization

product_line_custom
Intel® PAC
Napatech SmartNIC
category
User Guide

Input considerations

The time synchronization input interfaces of the NT SmartNICs are supplied with limited protection.

The time synchronization inputs on the NT SmartNICs do not fully support NT-PPS time synchronization output signals.

Warning: Connecting incompatible signal sources to NT time synchronization input interfaces might damage the NT SmartNIC hardware.

When a time synchronization input is configured for PPS signals, the rising edge is interpreted as on time.

The Tyco Industrial Mini connectors

The Tyco Industrial Mini connectors on the NT SmartNICs consist of both an SMA port and an RJ45 port. The connectors must be connected to one of the time synchronization adapters described in PTP-SMA time synchronization adapter and PTP-RJ45/SMA time synchronization adapter. For the SMA interfaces the specifications in Specification for MCX- and SMA-based inputs are valid. The RJ45 interfaces are normal Ethernet data ports.
Note: This connector does not apply to NT200A02 and NT200A01 SmartNICs.

Specification for MCX- and SMA-based inputs

This table specifies the time synchronization input interface for the MCX- and SMA-based inputs on the NT SmartNICs (the internal and external inputs, respectively).

Mode Type Parameter Value
Power off/ Interface off Termination 100 kΩ DC
Current in clamping circuit 60 mA @ 5 V input
Note: This only applies to external SMA-based inputs and not to internal MCX-based inputs.
PPS mode In Termination 50 Ω DC
Rise/fall time 0 – 30 ns
Input levels Rising edge, TTL levels
Pulse width 1 µs – 999 ms
Current in clamping circuit 130 mA @ 5 V input
Out Rise/fall 0 – 10 ns
Output levels Rising edge, TTL levels @ 50 Ω load
Pulse width 67 ms
NTTS mode In Termination 50 Ω AC
Rise/fall time 0 – 30 ns
Input levels LVCMOS 2.5 V levels
Pulse width Proprietary NT protocol
Current in clamping circuit 130 mA @ 5 V input
Out Rise/fall 0 – 10 ns
Output levels LVCMOS 2.5 V levels
Pulse width Proprietary NT protocol