Onboard SDRAM

Napatech Link™ Software Features

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Intel® PAC
Napatech SmartNIC
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Feature Description

SDRAM requirement

Frames from the receive pipeline can be stored in onboard SDRAM before transferred to the host memory, if needed, in order to await available host memory transfer.

Total memory size

The total memory size for all buffers in the onboard SDRAM is:

  • NT200A02: 12 Gbytes
  • NT200A01: 12 Gbytes
  • NT100E3-1-PTP: 8 Gbytes
  • NT80E3-2-PTP: 8 Gbytes
  • Intel® PAC A10 GX: 4 Gbytes
  • NT40A01: 4 Gbytes
  • NT40E3-4-PTP: 4 Gbytes
  • NT20E3-2-PTP: 4 Gbytes
Note: The total memory size for all buffers in the onboard SDRAM of an NT200A02 is 12 Gbytes. In the 2 × 40 Gbit/s FM image and the 8 × 10 Gbit/s FM image for NT200A02, only 1.5 Gbytes are used for packet buffering while 10.5 Gbytes are used for flow matching.

Protection of frames in onboard memory

Frames stored in the onboard SDRAM are protected by a CRC, in order to detect any data error. One or more frames are discarded in case of any CRC error, depending on the error type.

The number of discarded frames can be derived from the ingress and egress counters, once the traffic is stopped and the SDRAM is emptied.

SDRAM fill level events

Four specific SDRAM fill levels can be defined in the ntservice.ini file (see DN-0449). If the SDRAM is filled above one of these levels, an event is triggered. If the fill level decreases below one of these levels minus 10%, an event is triggered.