Flash Controller

Napatech Link™ Software Features

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Intel® PAC
Napatech SmartNIC
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Feature Description

In this section

This section describes the flash controller. The flash controller handles the interface from the host CPU to the flash devices. It allows the host to write and read the flash memories through the FPGA.

Primary and secondary image

The flash memory contains two separate FPGA images. A bit in the flash memory specifies which of the two images is the so-called primary image, and the other image is then the secondary image.

The primary FPGA image is expected to work in all servers, and is the first to be loaded to the FPGA after a power-up.

The secondary FPGA image is used as backup for the primary FPGA image, and for validation of a new potential primary FPGA image.

Image handling

The onboard FPGA images are updated and manipulated using the imgctrl tool. See DN-0487 for a detailed description of the image handling features of the imgctrl tool.