Ports, Flows, Host Buffers and Streams

Napatech Link™ Software Features

Intel® PAC
Napatech SmartNIC
Feature Description

Illustration of ports, flows, host buffers and streams

This figure shows the naming conventions used for the data flow through the SmartNIC and into the host memory.

Data flow through the SmartNIC and into the host memory

Frames from the network are received by physical SmartNIC ports. SmartNIC ports are numbered from 0 to the number of physical SmartNIC ports minus one.

The frames from the ports are merged in arrival time order.

When the frames have passed through the frame decoder, hash and filter, frames are categorized into flows. Flows are groups of frames with the same properties with respect to filtering, port numbers and hash values.

The multi-CPU distribution functionality maps the flows to host buffers. From 1 to 128 host buffers can be defined with dynamic segment size, and from 1 to 64 host buffers can be defined with static segment size.
Note: Dynamic segment size does not apply to Intel® PAC with Intel® Arria® 10 GX FPGA.

When data is transferred from the SmartNIC to the host buffers in user memory it is done via DMA.