Introduction

Multi-CPU Distribution

product_line_custom
Intel® PAC
Napatech SmartNIC
category
User Guide

In this document

This document describes the multi-CPU distribution functionality in SmartNICs with Napatech Software Suite.
Note: This document refers to functionality provided by Napatech SmartNICs with fourth-generation architecture (also referred to as 4GA) as well as by the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA running Napatech Link™ Capture Software. For users of Napatech SmartNICs with third-generation architecture (also referred to as 3GA), please refer to the appropriate documentation relevant for Napatech 3GA SmartNICs.

Overview

A SmartNIC with Napatech Software Suite can be configured to divide traffic received by the SmartNIC, in up to 128 host buffers with dynamic segment size and 64 host buffers with static segment size, and in up to 128 or 64 streams in the host computer. This allows multiple threads or processes, running on different CPU cores, to split the traffic processing. Once the streams are defined in the system host, there are a variety of ways to specify the distribution of traffic to the host buffers. These include: round-robin distribution, selection based on a variety of hash key types, and filter selection.
Note: Dynamic segment size does not apply to the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA running Napatech Link™ Capture Software.