Frames are processed by the IP blocks in the SmartNICs.
The frame processing pipeline
The figure below shows a high-level diagram of the frame processing pipeline. The received frames are processed by the functional IP blocks in the sequence shown in the figure below.
This table shows supported IP blocks for each SmartNIC.
Note: Table legend:
- FPGA image types
- C: Capture image
- CR: Capture/replay image
- CR2: Capture/replay 2 image
- SLB: Socket load balancing image
- FM1: Flow Management 1 image
- TM: Test and measurement image
- TM1: Test and measurement 1 image
- G: Gbits/s
- X: Supported.
- –: Not supported.
IP block | NT400D11 | NT200A02 | NT100A01 | NT50B01 | Intel® PAC A10 GX | NT40A11 | NT40A01 | NT40E3-4-PTP | NT20E3-2-PTP | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
2×100G CR | 2×100G CR | 2×100G FM1 | 2×100G TM | 2×40G CR | 2×40G FM1 | 2×40G TM | 2×40G SLB | 4×25/10G CR | 2×25/10G CR | 2×25/10G TM | 8×10G CR | 8×10G FM1 | 8×10G SLB | 2×10/1G CR | 4×25/10G FM1 | 4×25/10G TM1 | 4×10/1G FM1 | 4×10/1G TM1 | 2×25/10G TM1 | 2×10/1G TM1 | 1×40G CR AFU | 4×10G CR AFU | 4×10/1G CR2 | 4×10/1G C | 4×10/1G SLB | 4×1G CR | 4×10/1G CR2 | 4×10/1G CR | 4×10/1G C | 2×10/1G CR | |
Frame decoder | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
Categorizer and filter | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
Hasher | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
Correlation key | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | – | X | X | X | X | X |
Deduplication | X | X | – | X | X | – | X | X | X | X | X | X | – | X | X | – | X | – | X | X | X | X | X | X | X | – | X | X | – | X | X |
Load distributor | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
IP fragment handling | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | – | X | X | X | – | X | X | X |
Packet masker | X | X | – | – | X | – | – | – | X | X | – | X | – | – | X | – | X | – | X | – | – | – | – | – | – | – | – | – | – | – | – |
Header stripper | X | X | – | – | X | – | – | – | X | X | – | X | – | – | X | – | X | – | X | – | – | – | – | – | – | – | – | – | – | – | – |
VLAN insert | X | X | – | – | X | – | – | – | X | X | – | X | – | – | X | – | X | – | X | – | – | – | – | – | – | – | – | – | – | – | – |
Local retransmit | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | – | X | X | X | X | – | X |
Slicer | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
Slicer on locally retransmitted frames | X | X | – | – | X | – | – | – | X | X | – | X | – | – | X | – | – | – | – | – | – | – | – | – | – | – | – | – | – | – | – |
Rx buffer handler | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
Tx buffer handler | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
Tx scheduler | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |