Napatech Link-Capture™ Software Features

Intel® PAC
Napatech SmartNIC
Content Type
Feature Description
Capture Software Version
Link™ Capture Software 12.11

This section describes the principles of operation of the transmit on time stamp feature.

Packet descriptors

The packet descriptor for each frame to transmit includes a time stamp that can be used to control the time of transmission. The transmission time can be specified in one of the supported time stamp formats. The FPGA converts the packet descriptor time stamp format into the SmartNIC internal time stamp format so that the time stamp can be compared to the SmartNIC time to determine the time of transmission.

The Napatech standard packet descriptor includes a txPort port selection field (see Dynamic transmission configuration) and a txNow bit. The host application can force the transmission of a frame as soon as possible (ignoring the time stamp in the packet descriptor) by setting the txNow bit in the packet descriptor.

The PCAP descriptor does not include a TX port selection field or a txNow bit. For the PCAP descriptor, all traffic is assumed to be captured on one port, and in the absence of a txNow bit, txNow is considered set.

Host buffer to port configurations

To control the relative timing of frames transmitted on a given port, only one host buffer can transmit on the port. Configurations where a host buffer is transmitting on a single port (A) or on multiple ports (B) are supported.

tx_on_ts_configurations Rectangle P0 P0 Rectangle.2 P0 P0 Rectangle.3 P0 P0 Rectangle.4 P0 P0 Rectangle.5 P0 P0 Rectangle.6 P0 P0 Sheet.7 Rectangle.8 P0 P0 Rectangle.9 P1 P1 Rectangle.10 P0 P0 Rectangle.11 P1 P1 Rectangle.12 P0 P0 Rectangle.13 P1 P1 Rectangle.14 P0 P0 Rectangle.15 P1 P1 Rectangle.18 P0 P0 Sheet.17 Sheet.18 Sheet.19 (A) (A) Sheet.20 (B) (B) Rectangle.21 P1 P1 Rectangle.22 P1 P1 Rectangle.23 P1 P1 Rectangle.24 P1 P1 Rectangle.27 P1 P1 Rectangle.26 P1 P1 Sheet.27 Rectangle.30 P1 P1

Time order of frame sequence

All frames should be in chronological order, that is with increasing time stamps. If this is not the case, the relative timing between transmission of frames cannot be guaranteed.

Frame transmit condition

During initialization of a port for transmit on time stamp, a constant offset ∆ is loaded into a time offset register associated with the port. The usage of a time offset register in the FPGA allows the packet descriptor time stamp value to be used immediately without time stamp calculations in software.

A frame Px scheduled for transmission is transmitted as soon as the SmartNIC time T fulfills this condition:

T ≥ TPx + ∆

  • TPx is the time stamp of frame Px.

  • ∆ is a constant offset.

Calculate the constant offset ∆ as:

∆ = TA - TP0 + TD

  • TA is the SmartNIC time at initialization.

  • TP0 is the time stamp of the first frame to transmit; subsequent frames are transmitted relative to this reference frame.

  • TD is an additional offset that allows enough time for configuring the port for transmission and placing the first frames in the transmit buffer system.